Design analysis of LVDS connection AC coupling with capacitors - News - Global IC Trade Starts Here 工业

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LVDS (Low Voltage Differential Signaling) is a physical layer data interface standard defined by TIA/EIA-64 and IEEE 1596.3 standards and is designed for high speed, low power, and low noise point-to-point communications over 100Ω media with balanced impedance control. Like other differential signal standards, LVDS has much lower noise than single-ended signals due to the elimination of electromagnetic radiation. At the same time, external noise is coupled to the two lines as a common mode signal, which is suppressed as a common mode signal, so its noise immunity is much stronger than that of a single-ended signal. In addition, the output of the LVDS driver is current-driven, which reduces ground return and eliminates inrush current compared to voltage driving in other differential signal standards. Reducing the voltage swing (only ±350mV, PECL is ±800mV, RS-422 is 2V) enables LVDS to achieve data rates equivalent to PECL (>800Mbps), while consuming only one-tenth the power of PECL.

LVDS' high speed, low power consumption and low noise make it ideal for backplane interconnection of telecommunications and networking equipment, interconnects within 3G cellular base stations, and digital video interfaces. In addition to the above advantages, the LVDS serializer and deserializer (Figure 1) also saves a lot of space and money for system design. This solution can reduce the interconnect density by a factor of five, saving a lot of space and cost in 3G and other communication applications with a large number of boards.

The use of capacitors to achieve AC coupling of LVDS data connections has many benefits, such as level shifting, removal of common mode errors, and avoidance of input voltage faults. This article not only introduces the proper selection of capacitors, but also provides guidance for terminal topology, as well as common-mode fault analysis.

LVDS logic inputs are one of many existing logic standards. As long as the source can provide sufficient amplitude for the LVDS input, typically a differential of 100mV Vp-p, AC coupling provides the required level shifting. Figure 2 depicts a circuit diagram of a negative-voltage ECL logic that converts signals to LVDS logic after AC coupling.

Optimize common mode voltage

Another advantage of AC-coupled LVDS is that it allows the receiving IC to set its optimal common-mode voltage. Figure 3 shows a typical LVDS input circuit. A 1.2V internal reference voltage provides bias for the two high-impedance termination resistors. If the input is ac-coupled, the receiving IC can set the common mode voltage to the internal bias level.

Overvoltage protection

The LVDS signal is always AC-coupled in the automotive electronics serial deserializer (SerDes) link because this configuration prevents the car battery from being shorted. For any signal line that passes through the power distribution slot, a basic requirement is that it must be able to withstand shorting to the battery voltage without damage. With an AC-coupled LVDS link, there is only a brief high current pulse when the coupling capacitor is charged to the battery voltage. The peak amplitude of the current is a function of the actual impedance at the time of the short circuit. The duration of the current glitch is a function of the coupling capacitance and the LVDS input and output protection structure. Although the SerDes link does not work when it is shorted, it can resume operation when the short circuit fault is removed.

Figure 1: Typical application circuit for the serializer-deserializer.

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