Abstract: The field programmable logic device (FPGA) is used as the design carrier, and the hardware description language (VHDL) is the main expression. The QuartusII development software and the GW48EDA development system are used as the design tools to provide a taxi meter. Working principle and hardware and software implementation methods. At the same time, the taxi meter is subjected to timing simulation and hardware verification.
Keywords: taxi meter; FPGA; VHDL; Quartus II

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O Introduction With the improvement of people's living standards. Traveling by car has become a way of travel for many people; when choosing transportation, many people tend to have convenient and fast taxis. The taxi meter designed based on EDA technology is widely concerned because of its advantages of low price, safety, reliability and ease of use. In this paper, the field programmable logic device (FPGA) is used as the design carrier, the hardware description language (VHDE) is the main expression, and the taxi meter designed by QuartusII development software and GW48EDA development system is designed to realize the starting price. The functions of driving billing and waiting for billing can fully meet the requirements of taxi billing.

l Main functions of the taxi meter The functions that the taxi meter can implement mainly include billing and display functions.
The general cost is calculated based on the mileage and waiting time. The starting price of a taxi is 7.00 yuan. When the mileage is less than 3km, the fee is calculated according to the starting price; when the mileage is greater than or equal to 3 km, it is charged at 2.5 yuan per kilometer. When the waiting time is greater than or equal to 4 minutes, it is charged at 1.8 yuan per minute. Therefore, the total cost should be calculated as follows:
Total cost = starting fee + (mileage - 3 km) × mileage unit price + (waiting time - 4 min) × waiting unit price The main function of the display function is the mileage, waiting time and total cost. The display mileage of the car is displayed by two digits, and the display mode is “××”, and the unit is km. The metering range is 0 to 99 km, and the meter resolution is 1 km. The display waiting time is displayed in two digits and the display mode is “XX”. The timing range is 0 to 59 min, and the timing resolution is 1 mi-n. The final display total cost is displayed in four digits. The display mode is “XXX.X” and the unit price is yuan. The pricing range is from 0 to 999.9 yuan. The pricing resolution is 0.1 yuan.

2 Biller structure and working principle
2.1 The overall structure of the taxi meter The overall structure of the taxi meter is shown in Figure 1. It includes the divider module, metering module, pricing module and integer conversion BCD module.

2.2 Design of Frequency Division Module Since the GW48EDA development system has only two clock input ports, and the system requires three clocks, and the frequency of each clock signal is different, it is necessary to divide the existing clock signal.
FIG. 2 shows a second signal simulation diagram obtained by frequency division, and the input signal is a conversion signal of an integer converted to a BCD code. The frequency of the conversion signal is very high, which guarantees the integer conversion BCD
The code output and input do not cause too much delay. The simulation results prove that the design is correct.
Figure 3 shows the output signal of the wheel that is divided by 100 meters. The input signal is the driving wheel rotation signal. Because the number of wheels required to travel 100 meters is different for different wheel diameters, different wheels are classified and discussed. The simulated waveform shown in Figure 3 is the crossover result with a wheel diameter of 520 mm.
2.3 Metering Module Design According to the functional design requirements of the taxi meter, the cost is calculated based on the mileage and waiting time. When the mileage is less than 3 km, the fee is calculated according to the starting price; when the mileage is greater than or equal to 3 km, the meter is charged at 2.5 yuan per kilometer. In addition, when the waiting time is more than or equal to 4 minutes, it should be charged at 1.8 yuan per minute. Therefore, the travel charging enable signal clk_length and the waiting charging enable signal clk_time should be designed as required. Figure 4 shows the simulated waveforms of the two signals. It can be seen from Fig. 4 that when the taxi start signal start is active high and the waiting signal stop is low, the taxi is in a running state, and when the mileage is greater than or equal to 3 kilometers, the system will generate an effective The driving billing enable signal; when the taxi start signal start is active high, and the waiting signal stop is also active high, the taxi is in a waiting state, when the waiting time is greater than or equal to 4 minutes, it can be generated Effective waiting for the billing enable signal.

It should be specially stated here that because the Quartus II synthesizer does not support decimals, when designing the taxi fare, the unit of the RMB corner should be placed in one place and the yuan in ten. And so on, so that the synthesizer can be integrated.
2.4 Conversion module design Since the final price of the taxi is to be displayed by the 7-segment digital tube, the input signal of the 7-segment digital tube is high level 'l' or low level '0': and the front of the design Partially defines the data type of the price as an integer, thus requiring an additional integer to BCD code conversion circuit. Figure 5 shows the simulated waveform of the integer converted BCD code. As can be seen from Fig. 5, when the price of the integer type (pri-ce) is 8, the bit position of the BCD code becomes 8 after 8 clock cycles; and when the price (price) is 54, after 54 In the clock cycle, the ones bit of the BCD code becomes 4, and the ten bits of the BCD code become 5. It should be noted here that the conversion of the integer in FIG. 5 to the BCD code requires a delay of a period of time. The larger the integer data, the larger the delay generated by the conversion output. In order to realize the conversion of integer to BCD code in real time, it is necessary to increase the frequency of the converted clock signal (clk_convert). The 100-way frequency meter designed in Figure 2 is designed to reduce this time. In practical applications, you can also consider increasing the frequency of clk_convert and designing a higher division ratio.

3 Hardware verification of taxi meter This design uses GW48EDA system produced by Hangzhou Kangxin Electronics Co., Ltd. as the hardware verification system, and selects EP1K30TCl44-3 of Altera Company as the main control chip. The master chip is a field programmable logic device based on a lookup table structure, and its basic logic unit is a programmable lookup table. It enables the operation of combinatorial logic, while programmable registers enable sequential logic operations. Therefore, as long as the input and output pins in the overall design of the taxi meter are pin-locked, then recompiled and downloaded, the hardware verification of the taxi meter can be performed. Experiments show that this design can realize all the functions of the taxi meter, which proves that the design is correct.

4 Conclusion This article uses field programmable logic device (FPGA) as the design carrier, with hardware description language (VHDL) as the main expression, and QuartusII development software and GW48EDA development system as the design tools, so as to design with starting pricing, driving pricing and A taxi meter that waits for the pricing function. The results show that the design can achieve all the required functions. At the same time, because
The FPGA chip is small in size, low in power consumption, cheap in price, safe and reliable, and can be changed to change the price of starting, the price per kilometer and the price of waiting time, etc., and it is convenient to maintain and upgrade, and it is easy to make ASIC. The chip has a good application prospect.

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