SDSoC
Is it difficult to get started with FPGA SoC? SDSoC helps you to cross the "threshold" article, we introduce the revolutionary positioning of the SDSoC development environment, and its great advantages in improving the development efficiency. After reading this book, many developers who have previously failed to enter the Zynq FPGA SoC platform will be eager to try.
However, before entering the SDSoC, some basic concepts are still necessary to understand in advance. The first thing is to understand the SDSoC "platform" term.
A SDSoC design project is built on a "platform". The so-called "platform" consists of two parts: a hardware platform and a software platform. It is a basic system that can be reused for design and development.
The platform was created using standard Vivado, SDK, and OS tools. The hardware platform (HPFM) defines such things as processing system (PS), I/O subsystem, memory interface, etc. These tasks are all based on a well-defined port interface (AXI, AXI-S,, clock, reset, interrupt). ). The software platform (SPFM) defines the OS, device drivers, boot loaders, file systems, libraries, and so on.
Based on C/C++ source code customization and dedicated hardware and software, users can extend the platform.
The SDSoC uses the platform as an independent solution space, based on the resources provided by the platform to generate the IP for the solution. Each solution is tailored to one platform.
A file with the extension xpfm contains references to the location of the hardware descriptor XML file (HPFM) and software descriptor XML file (SPFM).
Figure 1 below shows a schematic of a SDSoC platform.
Figure 1, SDSoC platform schematic
Sometimes we call it a base platform that contains a Vivado project and a bootable software image.
The Vivado project contains interface IPs and related drivers that interact with the top-level SDSoC application. The basic platform usually uses development tools and SOM provided by Xilinx and Avnet.
Figure 2 shows the overall structure of a complete SDSoC design based on the underlying platform. The C/C++/SystemC function that needs to be accelerated becomes the IP in FPGA programmable logic (PL), while other functions remain in the processor system (PS). At the same time, SDSoC automatically generates interconnections between those IP and PS systems.
Figure 2, the complete SDSoC design structure based on the basic platform
Therefore, understanding the SDSoC “platform†is the basis for a comprehensive understanding of SDSoC-based development methods and processes, and it is a stepping stone for getting started quickly with SDSoC. In the following article, we will detail how to build the SDSoC hardware platform and software platform.
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